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[ pdf ] Understanding and Performing Precise Jitter Analysis

``` Download 55 times Topic under  Digital Logic Analyzers Source: www2.tek.com  File size: 0 File type: pdf Last download on: Mon Apr 03, 2017 03:07:50 PM Short Desciption: Introduction Jitter in the 100 ps range is negligible for an application with a 50 MHz clock having a nominal period of 20 ns. Within this data- valid window, you can have nanosecond rise and fall times, with setup times also in the nanosecond range. Summary: Jitter Basics Jitter is defined as either the deviation of a signalÂ’s transition from its ideal position in time or the timing variation from transition to transition. Jitter sources include power supply noise, ground bounce and Vdd noise. Ground bounce shifts the Vcc and Gnd levels in a circuit. Phased locked loops (PLL) are one type of circuit employed in a wide variety of designs that depend upon these reference levels for a stable frequency output. Shifts in the Vcc and Gnd level can easily change threshold crossing levels in a PLL, affecting the transition time and resulting in jitter. Crystal references are prone to thermal and mechanical noise. And crosstalk from adjacent lines can couple into the lines of interest. Whatever its source, jitter can significantly reduce margin in an otherwise sound design. For example, excessive jitter can increase the bit error rate (BER) of a communications signal by incorrectly transmitting a data bit stream. In digital systems, jitter can violate timing margins, causing circuits to behave improperly. Bookmark or share this info on Google+ and leave comment at below : ``` ``` ```

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